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19/05 Diksha
Talent acquisition manager at reqres

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Design Verification Role (8-18 yrs)

Any Location Job Code: 42472

Urgent Hiring for SoC Design Verification (DV) Lead || Bangalore

Job Title: SoC Design Verification (DV) Lead


Experience: 10+ Years


Location: Bangalore

 
Industry: Semiconductors / VLSI


CTC- Up to 65LPA

Job Description:

- We are looking for an experienced SoC Design Verification Lead to drive and manage verification activities for processor-based SoC designs. 


- The ideal candidate will have extensive hands-on experience in DV methodologies, strong expertise in ARM-based designs, and proven leadership in managing and mentoring large verification teams.

Key Responsibilities:

- Lead SoC and processor subsystem verification projects from planning to closure.

- Architect and develop verification testbenches using SystemVerilog and UVM.

- Drive test plan development, testcase creation, coverage analysis, and bug tracking.

- Work closely with architecture, design, and software teams to understand functional requirements and system-level scenarios.

- Bring up boot code, implement ISR, exception handling, and other low-level routines in C/Assembly.

- Validate functionality of Cache controllers, DMA, and memory management units.

- Ensure protocol compliance and integration correctness for AMBA protocols (AXI, AHB, APB).

- Manage and mentor a DV team of 10+ engineers; assign tasks, conduct reviews, and drive quality and schedule adherence.

- Collaborate with cross-functional teams across geographies for milestone deliveries.

Required Qualifications:

- 10+ years of experience in Design Verification, preferably with multiple full-chip SoC projects.

- Strong hands-on experience in ARM Cortex-A/M series designs.

- Proficiency in SystemVerilog, UVM, and testbench architecture.

- Experience writing test cases in C and Assembly.

- Strong understanding of SoC architecture, memory subsystems, and interconnects.

- Expertise in AMBA protocols (AXI/AHB/APB).

- Solid grasp of Cache, DMA, and memory management concepts.

- Proven leadership in handling at least 2- 3 SoC DV/Processor subsystem projects with sizable teams.

- Excellent communication, problem-solving, and organizational skills.

Preferred Qualifications:

- Experience with Tensilica Xtensa processor-based designs.

- Familiarity with formal verification, low power verification, and scripting (Python/Perl).

Education:

- Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or a related field.

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