FPGA Verification Engineer - RTL/System Verilog (4-12 yrs)
JD for FPGA Verification Engineer
- Verification of high speed FPGA ( FPGA RTL Verification is required), ASIC is added advantage
- Block/subsystem/chip level functional verification
- Implement verification environment independently using high level verification languages like System Verilog
- Understand and execute the existing verification flows and improve the framework
- Communicate and coordinate with designers and stake holders to verify design correctness
- Contribute to verification methodology development and implementation
Job Requirements
- 3 - 6 years of industry hands-on experience in verification
- Bachelors/Masters in Electronics Engineering
- Proven experience in high level methodology based verification on block/chip level
- Strong communication skills
- Knowledge of PCIe or similar protocol will be an added advantage
- Knowledge of FPGA design and development flow is a plus
- UVM methodology based implementation experience is desirable
- Experience in developing and implementing coverage driven verification plan will be a plus.
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