Executive HR at Source one
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Hardware Engineer - Physical Design (3-7 yrs)
- Thorough knowledge of the ASIC design timing closure flow and methodology.
- Expertise in STA tools (Primetime/Tempus) and flow.
- Knowledge of timing corners/modes, process variations and signal integrity related issues.
- Hands on experience in timing/SDC constraints debug.
- Proficient in scripting languages (TCL).
- Familiarity with backend related methodology and tools.
- Strong background in Constraint analysis and debug
- Self-starter and highly motivated