Manager HR at Spaak Super Tec Pvt Ltd
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Implementation Enginee - Synthesis & Timing closure (5-8 yrs)
Educational Qualifications : B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major.
Relevant Experience : 5 to 8 years
Location : Hyderabad
NP : Max 1 Month
Relevant Experience Job Description :
- Strong knowledge in IP/SOC design methodologies.
- Experience in working on real time projects and seen complete cycle of chip i.e. Specification to Silicon.
- Knowledge of RTL design in multiple projects with Verilog/ system Verilog and front-end design tools & flows
- Good experience in constraints development & analysis, Synthesis & Timing Analysis
- Strong knowledge on LINT, CDC, DFT concepts. Hands on Experience added advantage.
- Experience working on Low power synthesis and understands UPF
- IP development and coding using standard coding guidelines
- Strong knowledge of AMBA AHB/ AXI protocol
- Video/ Audio Codecs knowledge is an added advantage
- Strong debugging skills.
- Experience in scripting using TCL/PERL
- Strong Written and Verbal communication skills